1. Field of the Invention
The present invention relates in general to the field of computer systems, and in particular, to an apparatus and method for performing efficient processing of instructions.
2. Description of the Related Art
Efficient processing of instructions in processors results in increased system performance. However, the processing of instructions is not always optimized. For example, address computation in processors that conform to the Intel Architecture (IA) 32 format typically requires the addition of three values, namely, the segment base address, the base address of the address within the segment [hereinafter "base address"] and an offset. A 3-input adder(s) is typically used to provide such address computation. In some of the more aggressive processor designs, the performance of a 3-input add may require 2 processor clock cycles, while a 2-input add may be performed within a single processor clock cycle.
Increased address computation latency results in performance degradation, particularly in applications which exhibit a large number of address generation interlocks. Accordingly, there is a need in the technology for providing an apparatus and method for performing efficient processing of instructions, such as address computation, so as to avoid the aforementioned problems.